Chapter 1: About the FIR Compiler
Features
1–3
Automatically generating the code required for the Quartus II software to
synthesize high-speed, area-efficient FIR filters of various architectures.
Generating a VHDL testbench for all architectures.
Figure 1–3 compares the design cycle using a FIR Compiler with a traditional
implementation.
Figure 1–3. Design Cycle Comparison
Traditional Flow
Define & Design Architectural
Blocks
FIR Filter
FIR Compiler Flow
Define & Design Architectural
Blocks
FIR Filter Design
Design
6 Weeks
Determine Behavioral
Characteristics of FIR Filter
1 Day
Specify Filter Characteristics
to FIR Compiler Megafunction
Calculate Filter Coefficients
(MATLAB)
Determine Hardware Filter
Architecture
Design Structural or Synthesizable
FIR Filter
(FIR Compiler Assists in Area/
Speed Tradeoff)
Simulate
Synthesize & Place & Route
Simulate
Synthesize & Place & Route
Area/Speed Tradeoff
Features
The Altera ? FIR Compiler implements a finite impulse response (FIR) filter MegaCore
function and supports the following features:
The following hardware architectures are supported to enable optimal trade- offs
between logic, memory, DSP blocks, and performance:
Fully parallel distributed arithmetic
Fully serial distributed arithmetic
Multibit serial distributed arithmetic
Multicycle variable structures
Exploit maximal efficiency designs as a result of FIR Compiler hardware
optimizations such as interpolation, decimation, symmetry, decimation half-band,
and time sharing.
Easy system integration using Avalon ? Streaming (Avalon-ST) interfaces.
? May 2011
Altera Corporation
相关PDF资料
IP-NCO IP NCO COMPILER
IP-NIOS IP NIOS II MEGACORE
IP-PCI/MT64 IP PCI 64BIT MASTER/TARGET
IP-PCIE/8 IP PCI EXPRESS, X8
IP-POSPHY4 IP POS-PHY L4
IP-RIOPHY IP RAPID I/O
IP-RLDRAMII IP RLDRAM II CONTROLLER
IP-RSDEC IP REED-SOLOMON DECODER
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